1: /* General constants used by the kernel. */
2:
3: #if (CHIP == INTEL)
4:
5: #define K_STACK_BYTES 1024 /* how many bytes for the kernel stack */
6:
7: #define INIT_PSW 0x0200 /* initial psw */
8: #define INIT_TASK_PSW 0x1200 /* initial psw for tasks (with IOPL 1) */
9: #define TRACEBIT 0x100 /* OR this with psw in proc[] for tracing */
10: #define SETPSW(rp, new) */ \
11: ((rp)->p_reg.psw = (rp)->p_reg.psw & ~0xCD5 | (new) & 0xCD5)
12:
13: #define HCLICK_SHIFT 4 /* log2 of HCLICK_SIZE */
14: #define HCLICK_SIZE 16 /* hardware segment conversion magic */
15: #if CLICK_SIZE >= HCLICK_SIZE
16: #define click_to_hclick(n) ((n) << (CLICK_SHIFT - HCLICK_SHIFT))
17: #else
18: #define click_to_hclick(n) ((n) >> (HCLICK_SHIFT - CLICK_SHIFT))
19: #endif
20: #define hclick_to_physb(n) ((phys_bytes) (n) << HCLICK_SHIFT)
21: #define physb_to_hclick(n) ((n) >> HCLICK_SHIFT)
22:
23: /* Disable/Enable hardware interrupts. */
24: #define lock() intr_disable()
25: #define unlock() intr_enable()
26:
27: /* Interrupt vectors defined/reserved by processor. */
28: #define DIVIDE_VECTOR 0 /* divide error */
29: #define DEBUG_VECTOR 1 /* single step (trace) */
30: #define NMI_VECTOR 2 /* non-maskable interrupt */
31: #define BREAKPOINT_VECTOR 3 /* software breakpoint */
32: #define OVERFLOW_VECTOR 4 /* from INTO */
33:
34: /* Fixed system call vector. */
35: #define SYS_VECTOR 32 /* system calls are made with int SYSVEC */
36: #define SYS386_VECTOR 33 /* except 386 system calls use this */
37: #define LEVEL0_VECTOR 34 /* for execution of a function at level 0 */
38:
39: /* Suitable irq bases for hardware interrupts. Reprogram the 8259(s) from
40: * the PC BIOS defaults since the BIOS doesn't respect all the processor's
41: * reserved vectors (0 to 31).
42: */
43: #define BIOS_IRQ0_VEC 0x08 /* base of IRQ0-7 vectors used by BIOS */
44: #define BIOS_IRQ8_VEC 0x70 /* base of IRQ8-15 vectors used by BIOS */
45: #define IRQ0_VECTOR 0x50 /* nice vectors to relocate IRQ0-7 to */
46: #define IRQ8_VECTOR 0x70 /* no need to move IRQ8-15 */
47:
48: /* Hardware interrupt numbers. */
49: #define NR_IRQ_VECTORS 16
50: #define CLOCK_IRQ 0
51: #define KEYBOARD_IRQ 1
52: #define CASCADE_IRQ 2 /* cascade enable for 2nd AT controller */
53: #define ETHER_IRQ 3 /* default ethernet interrupt vector */
54: #define SECONDARY_IRQ 3 /* RS232 interrupt vector for port 2 */
55: #define RS232_IRQ 4 /* RS232 interrupt vector for port 1 */
56: #define XT_WINI_IRQ 5 /* xt winchester */
57: #define FLOPPY_IRQ 6 /* floppy disk */
58: #define PRINTER_IRQ 7
59: #define AT_WINI_IRQ 14 /* at winchester */
60:
61: /* Interrupt number to hardware vector. */
62: #define BIOS_VECTOR(irq) \
63: (((irq) < 8 ? BIOS_IRQ0_VEC : BIOS_IRQ8_VEC) + ((irq) & 0x07))
64: #define VECTOR(irq) \
65: (((irq) < 8 ? IRQ0_VECTOR : IRQ8_VECTOR) + ((irq) & 0x07))
66:
67: /* BIOS hard disk parameter vectors. */
68: #define WINI_0_PARM_VEC 0x41
69: #define WINI_1_PARM_VEC 0x46
70:
71: /* 8259A interrupt controller ports. */
72: #define INT_CTL 0x20 /* I/O port for interrupt controller */
73: #define INT_CTLMASK 0x21 /* setting bits in this port disables ints */
74: #define INT2_CTL 0xA0 /* I/O port for second interrupt controller */
75: #define INT2_CTLMASK 0xA1 /* setting bits in this port disables ints */
76:
77: /* Magic numbers for interrupt controller. */
78: #define ENABLE 0x20 /* code used to re-enable after an interrupt */
79:
80: /* Sizes of memory tables. */
81: #define NR_MEMS 8 /* number of chunks of memory */
82:
83: /* Miscellaneous ports. */
84: #define PCR 0x65 /* Planar Control Register */
85: #define PORT_B 0x61 /* I/O port for 8255 port B (kbd, beeper...) */
86: #define TIMER0 0x40 /* I/O port for timer channel 0 */
87: #define TIMER2 0x42 /* I/O port for timer channel 2 */
88: #define TIMER_MODE 0x43 /* I/O port for timer mode control */
89:
90: #endif /* (CHIP == INTEL) */
91:
92: #if (CHIP == M68000)
93:
94: #define K_STACK_BYTES 1024 /* how many bytes for the kernel stack */
95:
96: /* Sizes of memory tables. */
97: #define NR_MEMS 2 /* number of chunks of memory */
98:
99: /* p_reg contains: d0-d7, a0-a6, in that order. */
100: #define NR_REGS 15 /* number of general regs in each proc slot */
101:
102: #define TRACEBIT 0x8000 /* or this with psw in proc[] for tracing */
103: #define SETPSW(rp, new) /* permits only certain bits to be set */ \
104: ((rp)->p_reg.psw = (rp)->p_reg.psw & ~0xFF | (new) & 0xFF)
105:
106: #define MEM_BYTES 0xffffffff /* memory size for /dev/mem */
107:
108: #ifdef __ACK__
109: #define FSTRUCOPY
110: #endif
111:
112: #endif /* (CHIP == M68000) */
113:
114: /* The following items pertain to the scheduling queues. */
115: #define TASK_Q 0 /* ready tasks are scheduled via queue 0 */
116: #define SERVER_Q 1 /* ready servers are scheduled via queue 1 */
117: #define USER_Q 2 /* ready users are scheduled via queue 2 */
118: #define NQ 3 /* # of scheduling queues */
119:
120: /* Env_parse() return values. */
121: #define EP_UNSET 0 /* variable not set */
122: #define EP_OFF 1 /* var = off */
123: #define EP_ON 2 /* var = on (or field left blank) */
124: #define EP_SET 3 /* var = 1:2:3 (nonblank field) */
125:
126: /* To translate an address in kernel space to a physical address. This is
127: * the same as umap(proc_ptr, D, vir, sizeof(*vir)), but a lot less costly.
128: */
129: #define vir2phys(vir) (data_base + (vir_bytes) (vir))
130:
131: /* Translate a pointer to a field in a structure to a pointer to the structure
132: * itself. So it translates '&struct_ptr->field' back to 'struct_ptr'.
133: */
134: #define structof(type, field, ptr) \
135: ((type *) (((char *) (ptr)) - offsetof(type, field)))